In order to realize a highly integrated semiconductor device, various semiconductor elements that constitute the semiconductor devices such as transistors, capacitors, and various interconnections must be formed in a very narrow region. With a short distance between the components, insulation between the components should be reinforced.
In related art, as a means for electrically separating semiconductor elements that constitute a semiconductor device, a LOCOS type field oxide layer formed by locally oxidizing a silicon substrate may be used. However, in the LOCOS type field oxide layer, “bird's beak” regions generated during the process of forming the active regions may allow the semiconductor elements to partially invade an active region. This hampers efforts to realize a highly integrated semiconductor device.
Therefore, a field oxide layer that is formed in a small region and that has excellent insulation properties such as a trench type field oxide layer is required. In particular, shallow trench isolation (hereinafter, referred to as STI) may be used for this purpose.
Referring to FIG. 1, a related method of forming STI will be described as follows. A pad oxide layer 13 and a pad nitride layer 15 are sequentially formed in the silicon substrate 10.
After applying a photosensitive agent over the pad nitride layer 15, a photosensitive layer pattern (not shown) that distinguishes an active region from a field region of the substrate is formed by a photolithography process.
The pad nitride layer 15 and the pad oxide layer 13 are sequentially etched using the photosensitive layer pattern as a mask. In an adjunct process, the inside of the substrate 10 is etched to a predetermined depth to form a trench 18. After forming the trench 18, the photosensitive layer pattern is removed through a cleansing process.
Then, a thin STI lining oxide is formed in the trench 18 through a thermal oxidation process to modifies the surface of silicon. Then, a trench oxide layer 19 such as a CVD oxide using a TEOS oxidation film and a high density plasma CVD oxide is buried in the trench.
The trench oxide layer 19 is deposited over the entire surface of the pad nitride layer 15. Since the surface of the trench oxide layer is not even due to the unevenness there under immediately after the trench oxide layer is buried in the trench 18, the entire surface of the trench oxide layer 19 is planarized using a CMP process in order to perform subsequent processes.
Then, the pad oxide layer 13 and the pad nitride layer 15 over the substrate 10 are wet etched and removed so that the STI used as a device isolation layer is completed.
STI is designed to take up a small area over a highly integrated semiconductor device. In the semiconductor device, when critical dimension (CD) is very small, it becomes difficult to reduce the width of the photosensitive layer pattern for forming a trench to no more than a predetermined value due to limitations on the photolithography process.